RS485 Auto Enable in HW

[Prasad]

Dear Forum,

This is my first post on this forum. I am right now working on STR9 based platform that communicates over RS485 . In earlier version of the 485 Driver code, the Tx Enable was controlled in SW before Rx. But in the new version of this platform, the AutoEnable circuit (based on Transistor and RC )is controlling the Transmit enable. I am now porting the SW driver that was running in earlier platform and experiencing problems. This AutoEnable crcuit design is such that if any communication occur at less than 1Mbps, then the Tx will not work.

On the 485 line, we have 1 slave STR9 ( this has the autoenable circuit) and other master ATMega that has its USART1 configured at 115200 bauds.

For the driver in new platform , I do the below things.
1. Remove explicitly enabling and disabling the Tx Enable pin before and after Tx in my driver code
2.Only thing I take care is the echo , so I only diable the echo by diabling Rx interrupts before a Tx is made.

I would like to know from learned users whether I am doing right thing as above or not .

right now the communication is not working properly  between these 2 platforms.

Any hints on this please?

Thanks,
Prasad

[Jan Axelson]

Use a 'scope to watch the timing of the transmit-enable circuits and adjust the components as needed.

My article here might be helpful:

http://www.janaxelson.com/rs-485_circuits.htm

Jan

[Prasad]

Hello,
I post the scope pictures right here.

Regards,
Prasad

[attachment deleted by admin]

[Prasad]

Hello,

The scope captured the EN, RS485 A ,B when I made sample code for Tx of 6 bytes of data . I use Polled Tx and a Rx ISR to receive at 115200 bps.

Since Autoenable circuit frees the SW Designer of making disable/enable transmit , Now I dont use Enable/Disable Transmit pair in my Tx part of driver code. Besides this, I add to disable Rx before to Tx in the code.
My question is whether I need to take care of any special thing in my driver?

In actual scenario, the ATMega master sends request on the 485 at 115200 bps to get data from STR9 slave that is now also configured  to match 115200 and on the STR9 HW , we have the AutoEnable circuit . But on the ATMega side, the Enable is controlled in SW by a delay mechanism.

Can we really have such a scenario where in one Rs485 node, Enable is controlled in HW and in another node is controlled in SW?

Any pitfalls in exchanging data between these nodes and design consideration for this  kind of situation please?

Regards,
Prasad Ram Shrisha

[Jan Axelson]

You just need to be sure that only one transmitter is enabled at a time. If a node keeps its transmit-enable line active beyond the time needed to transmit, the next node to transmit will need to delay before sending.

Jan

[Prasad]

In my case there are 2 nodes on RS485 trying to send/receive data . If the transmit enable/disable is handled in HW as in my case,  then in the driver code, can I treat the 485 bus just like RS232 Tx/Rx or should I need to also handle something else like disabling the transmitter when I service the Rx interrupt in ISR and so on.

I am stuck up in this phase because the problem I am currently facing is that the Tx is not happening .I have a Tx ISR and I transmit when the Tx Fifo full flag is not set . Is this problem because I removed Tx Enable and Disable from my earlier code as now it is done in HW ?

Thanks,

[Jan Axelson]

In my case there are 2 nodes on RS485 trying to send/receive data . If the transmit enable/disable is handled in HW as in my case,  then in the driver code, can I treat the 485 bus just like RS232 Tx/Rx

Yes except if you have software-controlled nodes, before transmitting, the next node might have to wait for the previously transmitting software-controlled node to disable its transmitter.

Jan