Duration of AC stress evaluation

[rkalla]

What is the duration required for the AC Stress Evaluation from section  7.1.1 USB Driver Characteristics  or the USB2.0 spec? 
 The verbage reads:
"USB ports must be capable of withstanding continuous exposure to the waveforms shown in Figure 7-2 while in any drive state"

Does this imply the driver needs to tolerate at 6Mhz   +4.6/-1v swing for the life of the product?   Similar to the Short circuit withstand  test that was removed,
This will be hard to achieve for newer silicon  technologies like 32nm.

Thanks

[Tsuneo]

This will be hard to achieve for newer silicon  technologies like 32nm.

Why not?
Low-voltage core technology - ie. thin gate oxide just for high-speed core, high-voltage tolerant thick oxide for pin buffer - has been introduced in MPU silicon process first, so long ago. The application has extended to FPGA/CPLD. Nowadays, even many 8bit MCUs of new release apply this technology, for high-speed low-power consumption.

Tsuneo