Author Topic: Synchronous RS422  (Read 554 times)

dduley

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Synchronous RS422
« on: August 28, 2019, 12:39:37 pm »
Hi, I have been struggling with polarities on RS530/RS422 clock signals for an application at work that requires synchronous serial. We discovered that a few cables that were designed 15 years ago had the receive clock lines swapped thus inverting this signal. You touch briefly, in your book, on synchronous serial but really only as it relates to  SPI, I2C and Microwire. These types of interfaces are typically normal logic levels whereas RS530 is RS422. The issue is that if you flop the the -A and +B it effectively inverts the signal. You would think that this simply would not work but, in fact, much of the time it does work although with a drastically reduced timing window. In the application at work this worked for 15 years, although with frequent receive errors. A recent batch of boards, however, caused the system to completely fail. The board has many old TTL HCT parts and the new batch had chips that had a propagation delay that was .5ns faster than the previous batch. This serial link's clock transitions the data on the rising edge and samples the data mid-bit on the falling edge (opposite to the timing diagrams in the book). The faster driver caused the data to be sampled during the transition time in the grey area between a 0 and a 1.
I don't know if you are planning a 3rd edition of the serial port book but it would be great if you talked a little about other synchronous serial protocols like RS530 with expected timings and possible pitfalls.

I have many of your books and refer my staff to them when confused about serial port and USB issues.

Thanks!

Jan Axelson

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Re: Synchronous RS422
« Reply #1 on: August 29, 2019, 10:10:15 am »
Interesting information, not surprising that faster chips would increase problems. Thanks for posting this.

BasilNic

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Re: Synchronous RS422
« Reply #2 on: September 27, 2019, 07:34:26 am »
What's the reason for faster chips to create more problems like that exactly?

Jan Axelson

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Re: Synchronous RS422
« Reply #3 on: September 28, 2019, 12:51:07 pm »
As dduley said, the faster driver sampled the data sooner, causing the data to be sampled during the transition time in the grey area between a 0 and a 1, rather than when the logic level was stable.