Query reg data transfer for USB2.0

[njsimha]

I have a query regarding the data transfer calculation for USB.

Can someone please elaborate me how is the value of 480Mbps is decided for USB 2.0(which uses 125us frame size) as the transfer rate?

Also how is 5Gbps decided for USB 3.0?

[Jan Axelson]

From USB Complete (http://www.lvr.com/usbc.htm):

High speed’s rate of 480 Mbps was chosen for several reasons. The frequency is slow enough to allow using the same cables and connectors as full speed. Components can use CMOS processes and don’t require the advanced compensation used in high-speed digital signal processors. Tests of high-speed drivers showed 20–30% jitter at 480 Mbps. Because receivers can be designed to tolerate 40% jitter, this bit rate allows a good margin of error. And 480 is an even multiple of 12, so a single crystal can support both full and high speeds.

I believe 5 Gbps has to do with SuperSpeed's similarity to PCI Express.

Jan

[njsimha]

Hi Jan,
I read your book but still I couldn't understand this part of the explanation .

I would like to see if there is any mathematical formula that this value is derived.For example can we derive this value using the the frame size and the clock frequency used in USB2.0?

Also what is the clock frequency used in USb2.0?

Thanks.

[Jan Axelson]

I don't know of any mathematical formulas. I learned the info from an engineer at Intel.

Hosts and devices can use any clock frequency that enables them to meet the timing specs for the supported speeds.

Jan

[njsimha]

Hi Jan,
I read this info:

An oscillator is running at 480MHz which produces 60000 clocks at 125usec intervals.So the bandwidth is 7.5KB per 125us or 60KB/ms or 60MB/s or 480Mbps.

So basically it is purely from the oscillator that is used which decides the transfer rate.

But sorry to tell that I didnt understand your explanation.If you can explain in layman language it is very useful for me.

Thanks

[Jan Axelson]

Yes, the hardware can use a 480 Mhz oscillator to support a bit rate of 480 Mbps. But there is nothing in the spec that says you have to start with a 480 Mhz oscillator. For example, the PIC 18F4550 can use a variety of external oscillator frequencies (low and full speed only but the concept is the same).

Jan

[mdlayt]

There are three questions here:

1) why was the rate of 480MHz chosen (similarly for 5G)?
2) given 480MHz (or 5G), how does this relate to other numbers, such as effective bit throughput?
3) how does one implement the oscillator and clocking scheme?

At this point, the first two seem quite academic in nature.  But it would help to keep track of which is which.