I believe your implementation results in monstrous module :-)
Register to OpenCores, and download "USB 1.1 PHY"
http://www.opencores.org/project,usb_phyYou'll see bit stuff part in usb_tx_phy.v
This code is written in Verilog, but you'll become familiar with it soon.
USB 2.0 spec describes bit stuffing as follows,
7.1.9 Bit StuffingA zero is inserted after every six consecutive ones in the data stream before the data is NRZI encoded, to force a transition in the NRZI data stream.An implementation, which is faithful to this description, is as follows.
Combined with a shift register, bit stuff runs at bus clock.
Load
V
x|x|x|x|x|x|x|x| -----+
8bit shift register |
+---> |x|x|x|x|x|x| -------> NRZI encoder
| 6bit shift register
0 ----+
When above 6bit SR (Shift Register) is filled with ONEs, a ZERO is inserted at the next clock, instead of the output bit from 8bit SR. In this case, shift on 8bit SR is paused at the clock.
For variations,
- you may replace above 6bit SR with a counter, which counts contiguous ONEs.
etc.
Tsuneo