PORTS Forum
Ports and Interfaces => USB => Topic started by: Vinesh on May 03, 2012, 12:08:24 pm
-
In Host controller ULPI protocol specificatoin, while doing a TRANSMIT, the standard Specifies First we issue a TX command.
My Question is when does the PHY sample the TX command generated by the Host ?
Is it on the clock edge if it samples data[7:6] as 0b01 ? It looks like there is a skew in data lines D0,D1 for 10 ns. So I am wondering if command is accepted wrongly due to this ...
-
when does the PHY sample the TX command generated by the Host ?
It's at the rising edge of the ULPI bus clock.
The bus timing is described in this section of the ULPI spec (ULPI_v1_1.pdf, in http://www.ulpi.org/ULPI_v1_1.zip ),
3.7.2 Control and Data (p13)
Setup time of data in is 6.0ns (max), before the rising edge of the clock.
But you may be better to refer to the data sheet of your PHY.
For example, it's 5.0ns (min) for SMSC USB33xx.
Tsuneo