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Ports and Interfaces => USB => Topic started by: titan_amit on May 26, 2011, 02:09:21 am

Title: Implement Bit Stuffing in Hardware(VHDL)
Post by: titan_amit on May 26, 2011, 02:09:21 am

I am trying to develop a USB host controller. For that i need a module for bit stuffing. Though the logic seems quite simple, since we cant use loops in hardware design. I am facing problems. Can somebody suggest a better algorithm so that it can be implemented in hardware. This is the code I have written.

library ieee;
use ieee.std_logic_1164.all;
entity amit_bitstuff is
--generic (n,m : integer);
generic (n : integer :=96 ;m : integer := 112);
port ( din : in std_logic_vector(95 downto 0);
       --a2 : out std_logic_vector(n-7 downto 0);
       dout : out std_logic_vector(111 downto 0) --:= (others=>'0')
      
       );                                                   ----for n is in between 12 to 17   
end entity;
architecture arch of amit_bitstuff is
--       signal i : integer := 0;
--       signal j : integer := 0;
--       signal count : integer := 0;
       signal A : std_logic_vector(n-7 downto 0);
--       signal flag : std_logic := '0' ;


begin
   g0 :  for j in 6 to n-1 generate
         A(j-6) <= din(j-1) and din(j-2) and din(j-3) and din(j-4) and din(j-5) and din(j-6);
--         a2 <= A;
         end generate g0;
--      flag <='1' ;
 

  process(A)
  variable i : integer range 0 to 111 := 0;
  variable j : integer range 0 to 95 := 0;
  variable count : integer := 0;
  --variable A : std_logic_vector(n downto 1);
 
 
 
  begin
      
      dout(5 downto 0) <= din(5 downto 0);
      dout (m-1 downto n) <= (others=>'0');
      j := 6;
      i := 6;
      
            for j in 6 to n-1 loop
            if (A(j-6)='1' and count <= 0) then
            dout (i) <= '0';
            i := i+1 ;
            count := 5;
            dout(i) <= din (j) ;
            i:= i+1;
            
            
            else
            dout(i) <= din (j) ;
               i := i+1;
               count := count -1;
            
            end if;
         end loop;
   end process;
 end architecture;

Title: Re: Implement Bit Stuffing in Hardware(VHDL)
Post by: Tsuneo on May 26, 2011, 09:29:10 am

I believe your implementation results in monstrous module :-)

Register to OpenCores, and download "USB 1.1 PHY"
http://www.opencores.org/project,usb_phy

You'll see bit stuff part in usb_tx_phy.v
This code is written in Verilog, but you'll become familiar with it soon.


USB 2.0 spec describes bit stuffing as follows,
7.1.9 Bit Stuffing
A zero is inserted after every six consecutive ones in the data stream before the data is NRZI encoded, to force a transition in the NRZI data stream.

An implementation, which is faithful to this description, is as follows.
Combined with a shift register, bit stuff runs at bus clock.

Code: [Select]

    Load
      V
x|x|x|x|x|x|x|x| -----+
8bit shift register   |
                      +---> |x|x|x|x|x|x| -------> NRZI encoder
                      |     6bit shift register
               0  ----+
When above 6bit SR (Shift Register) is filled with ONEs, a ZERO is inserted at the next clock, instead of the output bit from 8bit SR. In this case, shift on 8bit SR is paused at the clock.

For variations,
- you may replace above 6bit SR with a counter, which counts contiguous ONEs.
etc.

Tsuneo