Strange last bit in SOF - edit

[ptrxtrnd]

Hi,
I am implementing an USB host on a custom board, using a stm32f427 controller.
I have some problems with enumerating an attached USB memory stick.
The device is detected and the host starts with sending control requests to get descriptors. But it seems the device does not reply on the request.
When measuring with an oscilloscope, I notice that the last bits of all packets look strange. The voltage level is half "one".
See image: https://drive.google.com/open?id=0B3wMeRPstoowY3VFN0hWYk8zVllzNk1UMzA3V1hpcFdNZjk4

What is that? Is it the EOP?
I  measure single ended.

/Peter

[Jan Axelson]

What speed?

A USB protocol analyzer can decode the traffic and help to isolate the problem.

http://janaxelson.com/development_tools.htm#analyzers

[ptrxtrnd]

Hi,
using the STM32 HS core running in FS.

After the control request is sent, the transaction error bit is set.

What can cause the strange voltage level? Is it the host (or device) that detects something is wrong, and pulls the bus low?

I have ordered an analyzer. Will get it today I hope.

[Jan Axelson]

I don't know the reason for what you're seeing.

What does the STM32's data sheet say the transaction error bit indicates?

[ptrxtrnd]

I have analyzed the communication with an protocol analyzer now. It says there is a CRC/bit stuff error on each SOF packet. And I guess the cause of that is the strange voltage level on the data lines.
But I still don't understand why the STM is outputting that.

[Jan Axelson]

Are you using a development board or a board of your own design?

[ptrxtrnd]

One discoveryF4 board and one custom board.
Everything is working on the discoveryF4 board. But on my custom board I get bit error in the last bits on each SOF packet.

The difference between the boards is that the discovery board runs the FS core of the stm32, but on my own board I run the HS core (in FS mode).
I guess the next thing to test is to use the FS core on my custom board also.