Corrections List for Parallel Port Complete by Jan Axelson 

Thanks to many alert and helpful readers for pointing these out!

Changes to all editions:

Page 4 (from Ron Ciren). At the end of the second to last paragraph, change 77Fh 
to 77Ah.

Page 12. (from Gustavo Dagostin da Silva). 
Change:
"The parallel port on some newer peripherals support a daisy-chain
protocol that allows up to eight devices to connect to a single port."
to:
"The parallel port on some newer peripherals support a daisy-chain
protocol that allows up to five devices to connect to a single port."
to match the final version of the IEEE1284-3 standard.

Page 15 (from Dean Cawthon). On line 1, change "1 Megabit" to "1 Megabyte."

Page 46, paragraph 2 and page 47, paragraph 3 (from Fernando Benito). Change 2.67 Mhz to 2.67 Mbytes.

Page 65. If a port is in Configuration mode, the program will give an 
"Invalid Property Value" error. To prevent this, add items 5 through 8 to 
the 
combo box created in Form_Load:

'Load the combo boxes with the ECP modes.
For Index = 0 To 3
    cboEcpMode(Index).AddItem "SPP (original)"
Next Index
For Index = 0 To 3
    cboEcpMode(Index).AddItem "bidirectional"
Next Index
For Index = 0 To 3
    cboEcpMode(Index).AddItem "Fast Centronics"
Next Index
For Index = 0 To 3
    cboEcpMode(Index).AddItem "ECP"
Next Index
For Index = 0 To 3
    cboEcpMode(Index).AddItem "EPP"
Next Index
'****************These are the new list items****************
For Index = 0 To 3
    cboEcpMode(Index).AddItem "reserved"
Next Index
For Index = 0 To 3
    cboEcpMode(Index).AddItem "test"
Next Index
For Index = 0 To 3
    cboEcpMode(Index).AddItem "configuration"
Next Index

Page 68. In the function GetEcpModeDescription, make the following changes:
Change
    Case  10
to
    Case 2
Change
    Case  11
to
    Case 3
Change
    Case  100
to
    Case 4
Change
    Case  110
to
    Case 6
Change
    Case  111
to
    Case 7

Page 88. Figure 5-3. S6 is pin 10. S7 is pin 11.

Page 89. -C3 is pin 17 (not 15).

Page 89. (from Royce Simmons) Figure 5-4. The sides of the four switches 
that are shown connecting to +5V should connect to ground. The pullups 
remain connected to +5V.

Page 92. (from Don Dalfior) -C3 is pin 17 (not 15). 

Page 94. Figure 5-6C is incorrect. One way to make the circuit match the truth table would be to do the following:
Eliminate the inverter at A.
Add an inverter in series between the NAND output and the base of the top transistor.
Add an inverter in series between the OR output and the base of the bottom transistor. 

Page 150. Under "Latching the Status Inputs," second paragraph, third 
line. Change "C3 goes low" to "-C1 goes low".

Page 212 (from Vuong Tran). Paragraph 2, second sentence:
Change "S3 (PaperEnd) to "S5 (PaperEnd)".
Change "S5 (nError)" to "S3 (NError)".

Page 243 (from Ulrich Klapper). The following is correct in the book, 
but not on the disk. Bits 5 and 3 are swapped. This is the correct code:

Bit0 = BitRead(LowNibble, 3)
Bit1 = BitRead(LowNibble, 4) * 2
Bit2 = BitRead(LowNibble, 4) * 4
Bit3 = BitRead(LowNibble, 7) * 8
Bit4 = BitRead(HighNibble, 3) * &H10
Bit5 = BitRead(HighNibble, 4) * &H20
Bit6 = BitRead(HighNibble, 5) * &H40
Bit7 = BitRead(HighNibble, 7) * &H80

Page 252 (from Ron Ciren). Figure 13-2. To match the signal names used in Figure 
13-1, C0 should be labeled (HostClk) and C1 should be labeled (HostBusy).

Page 258. Figure 13-3. In some printings, the direction of the buffers inside 
the 74LS244 and the two 74LS14 inverters are reversed. In the '244, pins 2, 4, 
6, 8, and 11 are inputs, so the top buffer image points left. Pins 13, 15, and 
17 are inputs, so the bottom buffer image points right. The 74LS14's point 
right. The pinouts are correct in all cases. Just the images are reversed.

Page 263 (from Ulrich Klapper). After this line:

    'Sub NibbleModeTransfer
Add:
    BitReset ControlPortData, 1

Page 270, 272 (comments from Dale Grover)
On both page 270 "Address write (forward transfer)" and page 272 "Data write (forward transfer)" there are steps stating "5.  When the peripheral is ready for another byte, it brings nWait low."  As far as I can tell, nWait is subject (in the 1284 EPP mode) to the "Tes" maximum timing of 125 nsec in all four transfers.  I think these steps should be, e.g. "5.  The peripheral brings nWait low."

The EPP (1284-1994), in using just one nWait signal, does not allow the host to determine the ability of the peripheral to respond to a particular transfer (i.e. data/address read/write) without initiating that transfer.  There is only one nWait line, and any combination of transfers might be valid or invalid at any particular time.  Instead, one may adopt one of two methods:

1.  A higher level mechanism allows the host to determine whether the peripheral is ready for a particular transfer. This might be implemented via a "status register" that is read at a specific address using the EPP protocol (i.e. a transfer that is "always" successful and never leads to a timeout).

2.  No attempt is made to determine the peripheral's readiness for a transfer.  The transfer is initiated, and the risk is always present that the peripheral may not be able to process the transfer (e.g., its input buffer might be full, or its output buffer might be empty), leading to a timeout when the device fails to bring nWait high within "Tel" (10 usec).

Page 298. The last sentence should end:
...the program transfers blocks of 32 bytes.

Page 302. To conform more closely to the IEEE-1284 standard, make the 
following changes in the DirectionRequest routine:

Replace all instances of S3 with S5. (The Basic-52 code in b52ecp.bas on 
the disk should also be changed to reflect this). Control port bit 1 should be 
reset in both cases: "pctoperipheral" and "peripheraltopc".

(And more on this topic from Jacob Nielsen) I have found that if I explicitly reset HostAck by writing the control register, then it will stay low even in ECP mode - in other words, control signals that are used by the ECP state machine should be written high before entering ECP mode. So if the code is changed according to the errata then reverse transfers fail, because the peripheral never receives acknowledge.

I have observed that if HostAck is set together with control bit 5 (direction) in PS2 mode, then HostAck is set low automatically when ECP mode is re-entered, and the handshake then works. So a way to make the original code 'ECP-compliant' would be to do the change to ECP mode before the nReverseReq/nAckReverse handshake is carried out. 

On the disk (From Victor Ishikeev):
In the CompByte example, in frmMain->Private Sub cmdWriteDataToPort_Click()
Replace:
ControlPortWrite ControlPortData, BaseAddress 
With:
ControlPortWrite BaseAddress, ControlPortData

About connecting HCT-family chips to parallel-port pins:
From Peter Mescher: 

I recently constructed a 72-pin I/O (32 out, 40 in) interface by
combining a couple of circuits in "Parallel Port Complete" (plus some
clever "glue" gates and minimal work on the C coding end).

The parts I received when ordering the 'HCT244's were TI SN74HCT244N
Octal buffers.  When the circuit is powered, they work beatifully.  They
source and sink great amounts of current, just as they are supposed to.

I first noticed a problem when I hooked some LED's into the TI
SN74HCT273N D FF's and turned off my power supply to go do some other
stuff.  However, the LED's stayed on!  (Not quite as bright as before,
but on nonetheless.)  When taking a current reading off Data pin 0, I
saw that the circuit was drawing 9mA through that pin!  (Through your
output multiplication scheme, there were 3 LED's hooked up to the 0
output of some D FF's.)  Luckily, my test bed is a spare
saved-from-the-dumpster 286 and a pile of old Hercules/LPT port combo
cards.

Upon investigation of TI's application notes, I came upon this one:
http://www-s.ti.com/sc/psheets/sdya009c/sdya009c.pdf

If you look at the section 2.3, "Behavior With the Supply Voltage
Switched Off", you will see, that at least for TI CMOS devices, when the
power is switched off, the I/O pins go into a low-impedance state!  They
even provide some helpful schematics showing you what happens.

Because I was using HCT buffers and delay FF's, the current had a
low-impedance path all the way to my circuit's output pins.  This means
that my HCT family Buffers and D FF's were powering LED's through the
data lines on the parallel port.  So instead of drawing uA's through the
port, I was taxing it at about four times your suggested maximum of
2.5mA.

TI's reasoning for this property was to protect against CMOS's notorious
sensitivity to static discharge.  I do not know if this is true across
manufacturers.

(The solution: use LSTTL chips instead. -Jan)

***

Changes only to books that are "copyright 1996" (not later) (page ii):

p. 22. Change "S4: SelectIn" to "S4: Select".
Change "C3: Select" to "C3: nSelectIn".

p. 83. Paragraph 2, 80291 should be 82091.

p. 92. Figure 5-5. D0-D7 are on pins 2-9 (not 1-8).

p. 113. Table 6-2. Make a total of twelve changes to the following rows: 
nError (nFault), S3, *15, *32, *4, *23, *29, *22 
PaperEnd, S5, *12, *12, 5, *24, *28, 23 
nSelectIn, /C3, *17, 36, 16, *25, 30, 34 
 
* indicates changed pin number 
 
p. 211. Figure 11-1. PtrBusy is shown initially high; it may be high or 
low. At nDataAvail, the label Peripheral Busy Status should read Current 
Peripheral Status.

p. 214. Paragraph 2: "...you exit Configuration mode by writing AAh to to 
port 3F0h."

p. 227. Figure 12-2A. The caption should end, "has returned high."

p. 290. Under Reverse Transfers, step 2 should read:
"At the host, HostClk (-C0) is high and HostAck (-C1) is high."

***

Changes to books that are "reprinted with corrections, 1997."

p. 193 (from Evan Suits). Figure 10-3.  Reverse the direction of 
the two "any buffer/drivers."

p. 199 (from Evan Suits). Figure 10-5. Reverse the direction of the 
buffers drawn inside the 74LS244. The pinouts are correct. Just the 
images are reversed.